07B
CY7C107B
CY7C1007B
1M x 1 Static RAM
Writing to the devices is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the input pin
(DIN) is written into the memory location specified on the ad-
dress pins (A0 through A19).
Features
• High speed
— tAA = 12 ns
Reading from the devices is accomplished by taking Chip En-
able (CE) LOW while Write Enable (WE) remains HIGH. Under
these conditions, the contents of the memory location speci-
• CMOS for optimum speed/power
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
fied by the address pins will appear on the data output (DOUT
)
pin.
Functional Description
The output pin (DOUT) is placed in a high-impedance state
when the device is deselected (CE HIGH) or during a write
operation (CE and WE LOW).
The CY7C107B and CY7C1007B are high-performance
CMOS static RAMs organized as 1,048,576 words by 1 bit.
Easy memory expansion is provided by an active LOW Chip
Enable (CE) and three-state drivers. These devices have an
automatic power-down feature that reduces power consump-
tion by more than 65% when deselected.
The CY7C107B is available in a standard 400-mil-wide SOJ;
the CY7C1007B is available in a standard 300-mil-wide SOJ.
Logic Block Diagram
Pin Configuration
SOJ
Top View
D
IN
28
27
26
1
2
3
4
5
6
A
A
A
A
A
A
V
CC
10
11
12
13
14
15
A
9
A
8
25
24
A
7
INPUT BUFFER
A
6
A
A0
23
22
5
A1
A2
A3
A4
A5
A6
A7
A8
7
8
9
10
11
12
13
NC
A
4
21
20
19
18
17
A
17
NC
16
A
A
3
A
19
A
2
18
512x2048
ARRAY
A
A
1
D
OUT
A
0
D
OUT
WE
GND
16
15
D
IN
14
CE
107B-2
POWER
DOWN
COLUMN
DECODER
CE
WE
107B-1
Selection Guide
7C107B-12
7C1007B-12
7C107B-15
7C1007B-15
7C107B-20
7C1007B-20
7C107B-25
7C1007B-25
7C107B-35
7C1007B-35
Maximum Access Time (ns)
12
90
15
80
20
75
25
70
35
60
Maximum Operating
Current (mA)
Maximum CMOS Standby
Current SB2 (mA)
2
2
2
2
2
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05030 Rev. **
Revised September 7, 2001
CY7C107B
CY7C1007B
Electrical Characteristics Over the Operating Range (continued)
7C107B-25
7C1007B-25
7C107B-35
7C1007B-35
Parameter
Description
Output HIGH
Voltage
Test Conditions
Min.
Max.
Min.
Max.
Unit
VOH
VCC = Min., IOH = −4.0 mA
2.4
2.4
V
VOL
VIH
VIL
IIX
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[1]
Input Load Current
VCC = Min., IOL = 8.0 mA
0.4
VCC + 0.3
0.8
0.4
VCC + 0.3
0.8
V
V
2.2
−0.3
−1
2.2
−0.3
−1
V
GND < VI < VCC
+1
+1
µA
µA
IOZ
Output Leakage
Current
GND < VI < VCC
,
−5
+5
−5
+5
Output Disabled
IOS
ICC
Output Short
VCC = Max., VOUT = GND
−300
−300
mA
mA
Circuit Current[3]
VCC Operating
Supply Current
VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
70
60
ISB1
Automatic CE
Power-Down
Current—TTL Inputs
Max. VCC, CE > VIH,
VIN >VIH or VIN < VIL,
f = f MAX
20
2
20
2
mA
mA
ISB2
Automatic CE
Max. VCC,
Power-Down
Current—CMOS Inputs
CE > VCC – 0.3V,
VIN > VCC – 0.3V or
VIN < 0.3V, f = 0
Capacitance[4]
Parameter
CIN: Addresses
CIN: Controls
Description
Test Conditions
Max.
7
Unit
pF
Input Capacitance
TA = 25°C, f = 1 MHz,
VCC = 5.0V
10
pF
COUT
Output Capacitance
10
pF
Note:
4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05030 Rev. **
Page 3 of 9
CY7C107B
CY7C1007B
AC Test Loads and Waveforms
R1 480Ω
R1 480Ω
5V
5V
OUTPUT
ALL INPUT PULSES
3.0V
GND
OUTPUT
90%
10%
90%
10%
ns
R2
255Ω
R2
255Ω
30 pF
5 pF
≤ 3 ns
≤ 3
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
107-4
(a)
(b)
107-3
Equivalentto:
THÉVENIN EQUIVALENT
167Ω
OUTPUT
1.73V
Switching Characteristics[5] Over the Operating Range
7C107B-12
7C107B-15
7C107B-20
7C107B-25
7C107B-35
7C1007B-12 7C1007B-15 7C1007B-20 7C1007B-25 7C1007B-35
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC
Read Cycle Time
12
3
15
3
20
3
25
3
35
3
ns
ns
ns
tAA
Address to Data Valid
12
15
20
25
35
tOHA
Data Hold from Address
Change
tACE
tLZCE
tHZCE
tPU
CE LOW to Data Valid
CE LOW to Low Z[6]
CE HIGH to High Z[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
12
6
15
7
20
8
25
10
25
35
10
35
ns
ns
ns
ns
ns
3
0
3
0
3
0
3
0
3
0
tPD
12
15
20
WRITE CYCLE[8]
tWC
tSCE
tAW
Write Cycle Time
12
10
10
15
12
12
20
15
15
25
20
20
35
25
25
ns
ns
ns
CE LOW to Write End
Address Set-Up to Write
End
tHA
tSA
Address Hold from Write
End
0
0
0
0
0
0
0
0
0
0
ns
ns
Address Set-Up to Write
Start
tPWE
tSD
WE Pulse Width
10
7
12
8
15
10
0
20
15
0
25
20
0
ns
ns
ns
ns
ns
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z[6]
WE LOW to High Z[6, 7]
tHD
0
0
tLZWE
3
3
3
3
3
tHZWE
6
7
8
10
10
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE and tHZWE is less than tLZWE for any given device.
7. tHZCE and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
Document #: 38-05030 Rev. **
Page 4 of 9
CY7C107B
CY7C1007B
Switching Waveforms
Read Cycle No. 1[10, 11]
t
RC
ADDRESS
t
AA
t
OHA
PREVIOUS DATA VALID
DATA VALID
DATA OUT
107-6
Read Cycle No. 2[11, 12]
ADDRESS
CE
t
RC
t
ACE
t
t
HZCE
LZCE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
PD
t
PU
V
CC
I
CC
SUPPLY
CURRENT
50%
50%
I
SB
107-7
Write Cycle No. 1 (CE Controlled)[13]
t
WC
ADDRESS
t
SA
t
SCE
CE
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA IN
DATA VALID
HIGH IMPEDANCE
DATA OUT
107-8
Notes:
9. No input may exceed VCC + 0.5V.
10. Device is continuously selected, CE = VIL.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05030 Rev. **
Page 5 of 9
CY7C107B
CY7C1007B
Switching Waveforms (continued)
Write Cycle No. 2 (WE Controlled)[13]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
DATA IN
DATA VALID
t
t
LZWE
HZWE
HIGH IMPEDANCE
DATA OUT
DATA UNDEFINED
107-9
Note:
13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 38-05030 Rev. **
Page 6 of 9
CY7C107B
CY7C1007B
Truth Table
CE
H
WE
DOUT
Mode
Power-Down
Power
X
H
L
High Z
Standby (ISB
Active (ICC
Active (ICC
)
L
Data Out
High Z
Read
Write
)
L
)
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY7C107B-12VC
Package Type
12
V28
V28
V28
V28
V28
V28
V28
V28
V28
V28
28-Lead (400-Mil) Molded SOJ
28-Lead (300-Mil) Molded SOJ
28-Lead (400-Mil) Molded SOJ
28-Lead (300-Mil) Molded SOJ
28-Lead (400-Mil) Molded SOJ
28-Lead (300-Mil) Molded SOJ
28-Lead (400-Mil) Molded SOJ
28-Lead (300-Mil) Molded SOJ
28-Lead (400-Mil) Molded SOJ
28-Lead (300-Mil) Molded SOJ
Commercial
CY7C1007B-12VC
CY7C107B-15VC
CY7C1007B-15VC
CY7C107B-15VI
CY7C1007B-15VI
CY7C107B-20VC
CY7C1007B-20VC
CY7C107B-25VC
CY7C1007B-25VC
Commercial
Commercial
Commercial
Industrial
15
15
20
25
Industrial
Commercial
Commercial
Commercial
Commercial
Contact factory for “L” version availability.
Package Diagrams
28-Lead (400-Mil) Molded SOJ V28
51-85032-A
Document #: 38-05030 Rev. **
Page 7 of 9
CY7C107B
CY7C1007B
28-Lead (300-Mil) Molded SOJ V21
Document #: 38-05030 Rev. **
Page 8 of 9
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C107B
CY7C1007B
Document Title: CY7C107B/CY7C1007B 1M x 1 Static RAM
Document Number: 38-05030
Issue
Date
Orig. of
Change
REV.
ECN NO.
Description of Change
**
109950
12/02/01
SZV
Change from Spec number: 38-01116 to 38-05030
Document #: 38-05030 Rev. **
Page 9 of 9
|